1. Field of the Invention
The present invention relates to an instruction fetch apparatus. More particularly, the invention relates to an instruction fetch apparatus and a processor for prefetching an instruction sequence including a branch instruction, as well as to a processing method for use with the apparatus and processor and to a program for causing a computer to execute the processing method.
2. Description of the Related Art
In order to maximize the processing capability of a pipelined CPU (central processing unit; or processor), the instructions within a pipeline should ideally be kept flowing without any hindrance. To retain such an ideal state requires that the next instruction to be processed be prefetched from a memory location where it is held to the CPU or into an instruction cache. However, if the program includes a branch instruction, the address of the instruction to be executed next to the branch instruction is not definitively identified until after the branch instruction is carried out. For this reason, an instruction fetch is put on hold; a pipeline stall takes place; and the throughput of instruction execution drops. Thus many CPU's have arrangements for suppressing pipeline stalls by performing prefetches despite the uncertainties stemming from the branches.
The typical prefetch scheme that can be implemented by simple hardware is called next-line prefetch (e.g., see Japanese Patent No. 4327237 (FIG. 1)). This is a technique for prefetching instructions in the order in which they are programmed. The basic pattern of the processor fetching instructions from a memory involves accessing the memory in sequentially ascending order of addresses. Thus the prefetching by hardware constitutes an attempt at storing the instruction of a given address into a cache and, on the subsequent assumption that the next cache line will also be used, storing automatically the next cache line as well.